As it becomes more difficult and expensive to keep the cost of technology node advancement under control, there is certainly a possibility that the pace of transistor shrinkage will begin to slow. An obvious question that many have asked themselves over many years is, “what happens then?”
While one can’t predict what technology advancements may save the day for transistor shrinkage and/or speed increase, one can predict what will happen to die size if chip complexity continues to increase while shrinkage begins to run out. One possible avenue for continued system shrink is already in the works–namely 3D ICs. Once the technology obstacles have been overcome (i.e. system test, heat transfer) and standards are well underway (namely for heterogeneous structures), 3D will be a viable path toward increasing system complexity while maintaining the same or smaller footprint in a product. However, ultimately, packaging as many features and functions onto the same die will likely win out in system performance and cost over a similarly functioning 3D IC. While there isn’t hard data to back up this claim, the fact that since 3D IC is really in it’s infancy in mass adoption, it is tough to argue either way.
450mm Die Packing Efficiency
So, if we reach the point where system complexity (if measured by number of transistors per die) begins to outstrip technology shrinks, we’ll end up gradually increasing die size, or increasing stacked die, or a combination of both. For many with history in the industry, you’ll recall that increasing die size was a driving force for the wafer size transitions in the 1980’s. The number of die which could be packed into a 150mm inch wafer was much greater than a 100mm wafer, for example. Though it is not as dramatic for 300mm vs. 450mm, the argument still applies.
A quick analysis by doing a brute-force die packing simulation in Matlab for 300mm and 450mm wafers shows the efficiency gain vs. die size. The simulation included square dies greater up to 35mm x 35mm in size (larger than a standard 22mm field) for steppers, and up to 26mm x 35mm (fixed 26mm field width) for scanners. The analysis examined the maximum number of die packed onto a 450mm wafer (die centered on the wafer, or corner centered, whichever provided more full die) as compared to the maximum number of die packed onto a 300mm wafer for each die size.
While the output of the analysis is somewhat noisy, a curve fit shows that overall, the packing efficiency for 450mm is substantial compared to 300mm wafers, increasingly so as die size increases. Even viewing the analysis at a maximum 22mm x 22mm stepper field size shows that an ~9% increase in packing efficiency can be expected. Similarly a 26mm x 33mm size shows about a 12% packing efficiency for 450mm wafers over 300mm wafers. This quick analysis’ point: if technology shrinks slow down and die size begins increasing, 450mm becomes an even more important part of the toolkit to increase overall manufacturing efficiency. A 10% to 12% improvement is significant, and is much greater than the standard, 2.7% improvement which has been used by the industry in most analysis (such as ISMI’s 2.31x multiplier vs. a raw area multiplier of 2.25x). However, lest anyone forget, a larger die is basically a larger target for defects, in other words, for a given defect density, you are more likely to have a chip that doesn’t yield as the die size increases. This yield reduction will reduce the overall improvement.
Above: 450mm Die Fit Video (Matlab Output of Simulation)