In his blog on EEtimes, Steve Schulz points out an obvious, but sometimes forgotten aspect to 450mm: EDA Tools. He raises a number of great points which I’d like to discuss further. I encourage you to read his blog on the subject. The link to his article is posted at the end.
450mm EDA Issues
Wafer flatness, progressively thinner device layers and the ensuing variations these cause are certainly issues at 300mm, but at 450mm, the problem is magnified considerably and will have an impact on device (transistor) design and performance. Steve Shulz addresses this in more detail in his article. As is the case somewhat with manufacturing equipment, you don’t know the difficulty until you actually start studying the problem, which given the complexities ahead, starting some EDA investigations soon seems to be in order.
Convergence of EDA Challenges
On top of these concerns about 450mm impact, there will be the convergence of a number of other challenges making 2018 a very significant date for semiconductor manufacturing. These include: 2.5-D and 3-D ICs (including stacked MEMS, RF, and Silicon Photonics), 10nm transistors, EUVL, increased SoC complexity. By 2018, 2.5-D and 3-D ICs will, hopefully, be using full 3-D floor planning, wherein the industry has moved past discrete heterogeneous stacks, to where advanced design capability will allow what would have been a large, planar SoC design to be optimally spread across multiple planes/chips. Likely, by 2018, 128-bit, Wide-I/O data paths have rippled throughout the system design, and MEMS are an integrated foundry offering for inclusion in a chip stack.
Now imagine the EDA toolsets, which fully integrate thermal, stress, and electromagnetic simulations into the mix, required to pull this off. With end-to-end design, verification, simulation—and software co-design—will a cloud-based, shared supercomputer be required? With 450mm semiconductor manufacturing equipment validation coming due in just a few years, the industry will need patterned wafers, and representative structures on these wafers. This means 450mm wafer cognizance on some level in EDA tools. It seems that one can’t wait too long to address the issues (known and unknown) at hand.
Success through Collaboration
With the challenges ahead, there should be little doubt that collaboration is going to be required. However, it’s not easy. As an example, it took many years for G450C, the chipmaker 450mm consortium, to come to fruition, and much of the delay was due to lack of trust between the partners. Part of the challenge deals with intellectual property (IP)—there’s a balance to collectively deciding to create a standard versus holding on tightly to your IP. Even collectively setting a date for the 450mm transition was tough as there was seemingly competitive advantage to having one’s own, independent target. However, convergence on a 2018 transition has helped provide the industry some needed direction. In the EDA arena, without significant IP, a company has little competitive advantage and the segment gets commoditized. But holding onto IP that serves no purpose other than to solely block competition (proprietary file formats and interfaces), rather than providing the industry “a better mousetrap,” can sometimes be quite counterproductive to industry progress and may even create animosity with your customer.
That’s where groups like Silicon Integration Initiative (Si2) come in. This EDA consortium’s members have been collectively solving hard problems for many years. They have one of the best participation and IP sharing / protection models in the industry—so much so that I’ve recommended their model to many other organizations. An advantage they have is that one can start at a member level and then pay only for those Coalitions and Technical Advisory Boards you wish to join: OpenAccess, DFM, Low Power, OpenPDK, Open3D, or Silicon Photonics.
I’d encourage you to read Steve’s Blog at EETimes, and if you are involved in EDA, seriously consider joining Si2 (if you haven’t already).
