In Albany, New York, G450C members and suppliers are gathering. Plans on 450mm R&D from Europe are likewise being announced. With all of this industry cooperation, how does a chipmaker differentiate on 450mm? The big levers driving cost-benefit, namely lithography and wafer size (for non-beam tools) are being worked on collectively. So, how does a 450mm-clubmember gain competitive advantage in this environment?
There are a few systems and tools that will play a role in cost reduction where differentiation can occur—these might not be so obvious at first blush. All else being equal (that is, all process tools available to all chipmakers in the market), two areas stand out: Automated Material Handling Systems (AMHS) and Inspection. The rest of this article will goes into why AMHS is so important and what could be done to stand out from the crowd.
AMHS Advantage
During the transition from 200mm to 300mm, material handling advances provided fab improvements in clean room and operator cost, as well as overall factory planning and efficiency. The Front Opening Unified Pod (FOUP) used in automated 300mm fabs for transporting wafers, moved the industry to a compartmentalized clean environment allowing cleanroom costs to drop substantially—on the order of 50% per square foot. Staff costs dropped, as operators were no longer needed to inefficiently taxi wafers through the manufacturing process. In fact, partly due to AMHS, “lights out” factories that were dreamed about became realities. AMHS allowed detailed, intelligent, real-time, automatic wafer-process planning for various products and lots, helping lead to the effective, high-product-mix mega-foundries of today.
AMHS Strategy for 450mm
Further AMHS gains are available for 450mm. Working individually on AMHS, rather than collectively sharing R&D with either the G450C partners or the semiconductor community at large, could result in a big competitive advantage. As there is good evidence to support the premise that all G450C players will be in the foundry business on some level by 2018, head-to-head competition is certain and some unique manufacturing advantages are required to differentiate. AMHS is bound to be one.
In “Making 450mm Work for Foundries” from 450mm.com, we read about the importance of a FOUP size smaller than the current SEMI Standard. Ten, seven, five, or even fewer wafers, is beneficial for high-mix, small lot manufacturing, not only from the improved cycle-time perspective, but also for stocking and storage. Given that the 25-wafer FOUP is the only existing industry standard, it is unlikely that the industry can collectively develop a smaller FOUP standard in time for the 2018, high-volume manufacturing transition. If your company is going to come out on top in the foundry game, given the timing and the state of the industry (i.e. heavily consolidated), the competitor chipmaker may not actually want nor advocate an industry standard on a smaller FOUP. As there’s only going to be a few chipmakers initially purchasing 450mm equipment, why not strike a deal with a AMHS company to develop a unique, smaller FOUP specific to your fab, leveraging the standards work in place…but tweaking it just a bit for, say, five-wafers.
But while you’re at it, don’t tell anyone else, especially anyone in G450C.
What would be the benefits? As already mentioned, there are cycle-time improvements for high-mix. Of course these same small lot improvements can be gained by inefficiently transporting fewer wafers in a large FOUP. But there’s more.
Less weight. A fully loaded five-wafer FOUP would weigh a little more than 20% the weight of a fully loaded 25-wafer FOUP. 25-wafer FOUP-based 450mm AMHS systems will have to carry much more weight than similar 300mm systems—the 450mm wafers are only bigger but also thicker. In fact, the whole fab infrastructure has to be beefed-up to handle the increase. Reducing the fully loaded FOUP weight by nearly 80% would have benefits that would ripple through the factory.
Faster acceleration with less stress. It’s simple Force = Mass x Acceleration. Our example, five-wafer FOUP can be accelerated faster, turned more quickly (less centrifugal force), and more rapidly cruise through a passing lane for a hot lot than a 25-wafer FOUP, all else being equal. Raising and lowering five-wafer FOUPs is less work as well.
I’m sure many can think of a number of other benefits to a 450mm FOUP designed for fewer wafers. This is one of those areas where an industry standard is likely not required. After designing the AMHS, the FOUP’s interface to the tool (load port) would also require modification. There’s no need to change wafer specifications. No change to the internal wafer-handling robot (besides slight reprogramming). And there’s potentially high competitive advantage. Plus the independent development doesn’t negatively impact the collective work done at G450C. If the chipmaker can, at the same time, develop some small-FOUP intellectual property that keeps others from using the exact same design (benefitting from the learning that has gone with it), all the better.
Of course, there’s no evidence that a chipmaker has such a plan for AMHS. But, if chipmakers were to ask, I’d encourage them to think about it…
Thanks for all the great articles John.
I’m a bit new to all these details so I have a few questions. What would be the reasoning behind a foundry wanting only 5 wafers in their FOUP instead of the standard 25? Is it because these so called ‘lots’ of 5 or 25 will end having the exact same architecture imprinted onto it?
If so, this is puzzling a bit puzzling! If TSMC would have orders from say 4 ARM chip designers, wouldn’t these companies order hundreds of thousands of chips in the first place? Or are orders always placed in smaller quantities?
So if TSMC was to receive an order for 250K chips, and a 450 mm wafer can produce say 1K of these chips, then why wouldn’t they use a 25 wafer FOUP in 10 lots? How will a 5 wafer FOUP, being able to produce 5K chips be beneficial when the client ordered way more than this amount?
Additionally, you mention the weight of a 5 wafer FOUP vs. the weight of a 25 wafer FOUP and how it could be cost effective. Aren’t we talking about pennies worth of economy here? And even if the FOUP accelerate/decelerate slower or faster, we are talking about potentially saving a few seconds, right? I don’t see how all of this could translate to a meaningful amount of savings for TSMC for example compared to Intel.
Thanks for your answers!
Hi Christian,
Good questions. Fortunately, there’s been some good studies and examples I can point you to. Regarding smaller lot sizes providing better cycle time and efficiency, there was a study by Daniel Babbs and Robert Gaskins from Brooks Automation done in 2008 that showed the improvements realized:
http://www.semi.org/en/About/SEMIGlobalUpdate/Articles/P042131
“According to Babbs and Gaskins, using the 25 wafer lot as the baseline and comparing all scenarios with 50 products, the five-wafer lot reduced average cycle time the most—by 13.7%. In addition, ‘this same five-wafer lot scenario with a 75% reduction in process tool setup time reduced the average cycle time by 24.5% from the baseline.’ They have several other interesting findings, including results on setup time, first-wafer delay, and implications for factory stability.”
Other studies have been done on small lots, including those from ISMI, who came to similar conclusions for 300 Prime scenarios. ITRS has some sections addressing it as well.
Regarding a company placing an order for 250k chips all at once… even if that were to occur, history shows TSMC hasn’t chosen to place all of their eggs in one basket, turning down such exclusive offers:
http://www.theverge.com/2012/8/29/3276229/apple-qualcomm-tsmc-exclusivity-bids
That doesn’t mean a company such as Intel, who seems to be open to some level of foundry-type work, wouldn’t go exclusive with a big win from a company such as Apple. In this case, 25-wafer FOUPs would come out just fine, just as you surmised. The more products on the same line, the less true this would be. Note the Brooks study assumed 50 products. Not unreasonable for a foundry or for chipmakers with a number of products.
Finally, the big issue with weight for the larger FOUP size is that one has to beef up everything, all fab structure, transport, etc. And similar FOUP acceleration generates five times the force. The speed gained? You’re right, likely not much and no real cost savings. However, the cost savings on bigger motors, structural, etc., is nontrivial. A few years ago we had a number of discussions on the 450mm AMHS system weight impact within SEMI Standards, primarily led by the SEMI Japan member companies, so it’s not a new problem to be brought up.
Thanks for your comments,
John