Is 450mm over? Not for good. At some point, technology, market, and the resulting economic changes will inevitability bring the discussion, and likely, the development, back. However, the New York-based, 450mm global consortium, G450C is done.
According to an article in the Times Union:
In an effort to put some type of positive spin on the developments, Empire State Development (ESD) spokesman Jason Conwall stated,
However, for anyone who is aware of the history of G450C, “developing wafer technology” was not the end goal. Setting up bona-fide 450mm fabs was the objective and this was the major focus of the second phase of the project. A commitment to build a 450mm fab in New York was a requirement for participation in phase two, which will (now) not be happening.
The demise was due to the inevitable realization that improvements can still be made to 300mm technology, rather than moving to the next semiconductor wafer size.
Another article in the Times Union states:
This is not a surprise. The 300mm Prime program and opportunities for continued efficiency improvements were discussed years ago.
In reality, there are many factors that led to the strike-out of G450C. Here’re a few.
At the beginning of G450C, Intel had forecast and anticipated increased demand for their processor. This prediction was based upon the underlying assumption for high demand of personal computers. However, the industry had not planned for the heavy demand for smart phones and tablets, and how these would eat into consumer spending for desktop and laptop computers. While Intel attempted to gain a foothold in portables devices, this never truly materialized. ARM designs have emerged as the principal leading processors for portable, wearable, and Internet-of-Things (IoT) devices. Thus upending Intel’s need for the silicon area provided by a 450mm fab.
Technology advancements and project timing also had a big impact on 450mm’s viability. G450C members, as a whole, did not fully anticipate the impact that monolithic 3D IC would have on demand for silicon area—specifically for memory chips. Companies, such as G450C-member Samsung, have been able to stack many layers of transistors on the same die (up to 48, so far). Combine this with almost immediate slips in G450C schedule, which allowed Extreme Ultraviolet Lithography (EUVL) to precede 450mm in availability, and transistor shrinks outpacing increases in IC complexity, and the predicted silicon area demand increase was curtailed.
Strike Three, You’re Out
If G450C wasn’t already over by 2016, the demise of Alain Kaloyeros, the former president and CEO of SUNY Polytec Institute, who has been indicted on both federal and state charges, has put doubts on SUNY’s ability to ethically manage consortia, such as SEMATECH and G450C—and the damage has spread beyond SUNY, impacting the ability of New York to attract new semiconductor business.
Intel, Samsung, and TSMC pulled out of SEMATECH in 2015. With G450C being dismantled, it’s now every company for themselves in terms of manufacturing R&D. Perhaps, with the continued industry consolidation, aggregated R&D dollars, as well as project-focused research organizations, such as imec, there will no longer be a place for large manufacturing consortia like G450C or SEMATECH.
With increased chip complexity (resulting in either increased die size and/or increased number of stacked die), eventual limitation to stacked transistor layers available through monolithic 3D, and slowing of transistor shrinkage (and increased cost), demand for silicon area will again begin to increase. The issues of efficiently meeting increased silicon demand, and, along with it, increased number of semiconductor fabs, will eventually have to be answered. Therefore, basic research into 450mm manufacturing should be continued to ensure it is a viable alternative at such a time that the market is truly ready to consider it as an option.